Semantic Inconsistency in Intermediate FIRRTL File During Compilation: Incorrect reg Emission Instead of node and Loss of Memory readUnderWrite Behavior

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**
Chisel Version: v3.5.6
FIRRTL Version: v1.5.6
Treadle Version: v1.5.6

We ran the official tests for each of the following cases (without any modifications), and then examined the `.fir` files in the `test_run_dir`. We observed inconsistencies between the `.fir` files and the source code. The details are provided below.

1. **ShiftResetTester**
- **Source Code**: `src/test/scala/chiselTests/Reg.scala`, Line 54
- **Description**: When `n = 0`, the register `sr` should have a constant value, which should be compiled to a `node`. (This is observable when emitting FIRRTL, where the translation results in a `node`.) However, when emitting Verilog (which generates a `.fir` file in the same directory), the register `sr` is compiled to a `reg`, leading to an inconsistency with the source code. Initially, the value in `reg sr` is either random or zero (depending on the settings), rather than the expected constant value.

2. **ShiftTester**
- **Source Code**: `src/test/scala/chiselTests/Reg.scala`, Line 44
- **Description**: This issue is similar to that in **ShiftResetTester**.

3. **SyncReadMemWriteCollisionTester**
- **Source Code**: `src/test/scala/chiselTests/Mem.scala`, Line 37
- **Description**: When emitting to Verilog, the memory `readUnderWrite` behavior is lost in the `.fir` file generated in the same directory.

**What is the current behavior?**
There are cases of semantic inconsistencies between the `.fir` intermediate files generated by Chisel's `emit verilog` and the source code (including incorrect compilation and loss of semantic information).

**What is the expected behavior?**
The semantic behavior of the `.fir` intermediate files generated by Chisel's `emit verilog` is consistent with the source code.

**Please tell us about your environment:**

- version: `v3.5.6`
- OS: `Ubuntu 24.04 LTS`

**Other Information**

Use `emit verilog` to generate the `.fir` in the same directory (`test_run_dir`) instead of directly using `emit firrtl`. I observed that in the FIRRTL repository source code, in `src/main/scala/firrtl/ir/Serializer.scala` at Line 303, the `readUnderWrite` field is lost during the emission.

**What is the use case for changing the behavior?**
I have mentioned it before: the official test code for `ShiftResetTester`, `ShiftTester`, and `SyncReadMemWriteCollisionTester` in the Chisel v3.5.6 repository.