Need for explicit widths in BlackBox parameters

Hello!

There seems to be a need for being able to explicitly define how wide you want your verilog parameters to be when using a Verilog component as a blackbox. Consider the case where you have a module with parameters `ADDR({ADDR1, ADDR0})` and `.ADDR_COUNT(2)`. Say your addresses are `{0x0100_dead, 0x0000_beef}` or something. If you define these addresses in chisel, The generated verilog parameters will crop the top 4 leading 0s in the address, which translates to `0x100_dead0000_beef`.

Thats all fine and well. The problem is now if you attempt to access the top 32 bits of the parametrized address, the simulator may or may not fail. Verilator, for instance, fails with an error saying that it does not support invalid bits for parameters.

I cant think of a better solution than providing support for explicit widths in verilog parameters via the chisel code. The verilog assuming it has all 64 bits is a pretty fair assumption, so I dont think its at fault here. I also think its probably for the best for the simulator to fail in this case.

Currently, I've resorted to padding a dummy 1 to my address fields parameter. If there is a better solution, I would love to hear it. Thanks. Take care.