chipsalliance / chipsalliance/chisel

Layers not emitted when used as colors of probes with separate elaboration

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Scala
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Description

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

1. Checkout this commit of Chisel (small change to test to demonstrate issue):

https://github.com/chipsalliance/chisel/commit/49325496999148dc3fe48c093a16811134715cfb

2. `testOnly chiselTests.experimental.hierarchy.SeparateElaborationSpec` (I did this by launching `sbt` and entering this at the prompt)

**What is the current behavior?**

Errors due to generated FIRRTL using layers that aren't declared:

```
[info] src/test/scala/chiselTests/experimental/hierarchy/Examples.scala:43:23: error: probe port 'p' is associated with layer '@A', but this layer was not defined
[info] @public val p = IO(probe.Probe(UInt(width.W), A))
```

**What is the expected behavior?**

All used layers are emitted, no error when using layer-colored probes in this way.

**Please tell us about your environment:**

**Other Information**

**What is the use case for changing the behavior?**

Contributor guide

Open the contributing guide

Research direction

Start by checking the reproduction commit and run `testOnly chiselTests.experimental.hierarchy.SeparateElaborationSpec` from sbt. Inspect `src/test/scala/chiselTests/experimental/hierarchy/Examples.scala` around line 43 and the separate-elaboration path. Done means the test no longer errors because layer-colored probes use layers that are emitted and declared.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
compilers
Issue type
Bug
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Clearly specified
Newbie friendliness
48/100

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