chipsalliance / chipsalliance/chisel

bundleWithABoolProbe := 0.U.asTypeOf(bundleWithABoolProbe) results in illegal firrtl

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bug
Dominant language
Scala
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Description

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

**What is the current behavior?**

Consider the following:
```
class BundleWithAProbe extends Bundle {
val tap = Probe(Bool())
}
class TestMod extends RawModule{
val a = IO(Output(new BundleWithAProbe()))
a :#= 0.U.asTypeOf(a)
}
ChiselStage.emitCHIRRTL(new TestMod)
```

This successfully emits illegal firrtl:

```
circuit TestMod :
...
public module TestMod : @[src/test/scala/chiselTests/ProbeSpec.scala 751:11]
output a : { tap : Probe>}

define a.tap = UInt<1>(0h0)
```

**What is the expected behavior?**

Not sure. This should at minimum not emit illegal firrtl.
If you do this without a Bundle, you get an error like:
```
mismatched probe/non-probe types in TestMod.a: IO[Bool] and Bool(false).
[error] a :#= 0.U.asTypeOf(a)
```

And if you do it for a Probe of a Bundle you get an even better error before you even try to do the connect, which is:

```
"Cannot create Const of a Probe."
```

It should probably throw an error, making it the user's responsibility to somehow drive the probe fields to probes-of-Wires that are initialized to 0, but that could be quite annoying and a helper API to do that might also be useful.

**Please tell us about your environment:**

commit: cf42ac7cb2cbca93056f025d6322b216228450e6
Date: Mon Sep 9 12:57:04 2024 -0700

**Other Information**

**What is the use case for changing the behavior?**

Chisel should generally not emit invalid firrtl

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