Path values do not work with multiple instantiation

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

Consider the following Chisel:
```scala
//> using repository "sonatype-s01:snapshots"
//> using scala "2.13.14"
//> using dep "org.chipsalliance::chisel:7.0.0-M2+66-a1c35ad8-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin:7.0.0-M2+66-a1c35ad8-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.util.experimental.InlineInstance
import chisel3.experimental.hierarchy._
import chisel3.properties._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

class Intf extends Bundle {
val in = Input(UInt(8.W))
val out = Output(UInt(8.W))
val path = Output(Property[Path]())
}

@instantiable
class Child extends Module with InlineInstance {
@public val intf = IO(new Intf)

val r = RegInit(0.U)
r := intf.in
intf.out := r

intf.path := Property(Path(r))
}

class Top extends Module {
val intfs = IO(Vec(2, new Intf))
val c0 = Instantiate(new Child)
val c1 = Instantiate(new Child)

intfs(0) :<>= c0.intf
intfs(1) :<>= c1.intf
}

object Main extends App {
println(
ChiselStage.emitSystemVerilog(
gen = new Top,
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info", "-default-layer-specialization=enable")
)
)
}
```

**What is the current behavior?**

This errors in firtool with:
```
.../chisel-example.scala:24:18: error: duplicate identifier found
.../chisel-example.scala:24:18: note: other identifier here
```

Note that this requires both the Inlining and the D/I Instantiate to manifest.

**What is the expected behavior?**

This should work, the path should be materialized in `Child` and threaded through to the top.

**What is the use case for changing the behavior?**

It should be possible to create `Path` values.