How to access chisel-generated modules using SystemVerilog interface

**Type of issue**: Feature Request

**Is your feature request related to a problem? Please describe.**

I am currently working with Chisel 6 and would like to access a module created in Chisel using the SystemVerilog interface syntax.

As far as I know, CIRCT's SV dialect contains enough operations for interfaces and a build process for the SV language. Nevertheless, it seems that Chisel does not yet support the functionality related to systemverilog interfaces.

In order to use SystemVerilog interface operations, it seems like Chisel would need to implement the interface statement in the sv dialect, but I'm not an expert on Chisel, so it would be difficult to use CIRCT's additional operations without some guidance.

Can you provide any resources or guidance on how to add these operations? Any guidance or documentation related to extending Chisel to support CIRCT's additional operations would be very helpful.

Thank you in advance for your help.