Module initialization test fails with ChiselSim while worked on chiseltest

I have a module and test below that uses module initialization value which works and tests fine under chiseltest but when ported over to ChiselSim, it started to fail.

```scala
// Run with scala-cli test thisfile.scala
//> using scala 2.13.14
//> using dep org.scalatest::scalatest:3.2.19
//> using dep org.chipsalliance::chisel:6.4.0
//> using dep edu.berkeley.cs::chiseltest:6.0.0
//> using plugin org.chipsalliance:::chisel-plugin:6.4.0

import chisel3._
import org.scalatest._

import flatspec._
import matchers._

class PCPort(bitWidth: Int = 32) extends Bundle {
val dataIn = Input(UInt(bitWidth.W))
val PC = Output(UInt(bitWidth.W))
val PC4 = Output(UInt(bitWidth.W))
val writeEnable = Input(Bool())
val writeAdd = Input(Bool()) // 1 => Add dataIn to PC, 0 => Set dataIn to PC
}

class ProgramCounter(regWidth: Int = 32, entryPoint: BigInt = 0)
extends Module {
val io = IO(new PCPort(regWidth))
val pc = RegInit(entryPoint.U(regWidth.W))
when(io.writeEnable) {
pc := Mux(io.writeAdd, (pc.asSInt + io.dataIn.asSInt).asUInt, io.dataIn)
}
io.PC4 := pc + 4.U
io.PC := pc
}

// Use the following to run the test using ChiselSim
import chisel3.simulator.EphemeralSimulator._
class ProgramCounterSpecChiselSim extends AnyFlatSpec with should.Matchers {
it should "initialize to 0" in {
simulate(new ProgramCounter()) { c =>
c.io.PC.peek().litValue should be(0)
}
}
it should "initialize to 0x00400000" in { // This fails here but works on chiseltest
simulate(new ProgramCounter(entryPoint = 0x400000)) { c =>
c.io.PC.peek().litValue should be(0x400000)
}
}
}

// Use the following to run the test using chiseltest
// import chiseltest._
// class ProgramCounterSpecChiselTest
// extends AnyFlatSpec
// with ChiselScalatestTester
// with should.Matchers {
// it should "initialize to 0" in {
// test(new ProgramCounter()) { c =>
// c.io.PC.peek().litValue should be(0)
// }
// }
// it should "initialize to 0x00400000" in {
// test(new ProgramCounter(entryPoint = 0x400000)) { c =>
// c.io.PC.peek().litValue should be(0x400000)
// }
// }
// }
```

It might be my own code logic that is wrong but it's strange it started failing when I ported to ChiselSim. The Module works fine on simulation and FPGA.