ChiselSim improvements to close the gap to chiseltest

ChiselSim Improvements

I started porting some tests from chiseltest to ChiselSim and found some usability gaps that could be improved. Also some error:

- [ ] Having a simulator which allows generating VCD Files (Addressed on #4201)
- [ ] Error on some Module and Memory initialization (needs further investigation)
- [ ] Have method extensions in the PeekPokeAPI that generates native Scala types like `peekLit` instead of `peek().litValue` like [sample1](#sample1).
- [ ] Handle ChiselEnum in Peek. Allow something like `c.io.DecoderPort.inst.peek() should be(inst)` instead of `c.io.DecoderPort.inst.peekValue().asBigInt should be(inst.litValue)` where `inst` is a ChiseEnum - (Reported on #4208)
- [ ] Have the ability to peek into SubModules like BoringUtils.bore exposed thru `chiseltest.experimental.expose` like [Observe.scala](https://github.com/ucb-bar/chiseltest/blob/82993eb0c0c19c5da95c5b60e214d3594414b102/src/main/scala/chiseltest/experimental/Observe.scala#L12)
- [ ] Verilator error on tests which have Modules with `chisel3.experimental.Analog` ports (#4202)

**Refs:**

Sample 1:

> ```scala
> // Scala 2 extension methods for Chisel Data types converting peek().litValue to peekLit
> object ObjectUtils {
> // For UInt and SInt
> implicit class UIntLitValue(u: UInt) {
> def peekLit: BigInt = u.peek().litValue
> }
> implicit class SIntLitValue(s: SInt) {
> def peekLit: BigInt = s.peek().litValue
> }
> // For Bool
> implicit class BoolLitValue(b: Bool) {
> def peekLit: Boolean = b.peek().litToBoolean
> }
> }
> ```

Start by checking the remaining checklist items and the referenced issues #4201, #4208, and #4202, then read the PeekPokeAPI and chiseltest's experimental Observe.scala. The issue needs to be split into focused tasks, each with a specific API or simulator behavior and a clear completion criterion.

Written by the indexing model from the issue text.