Modules with `chisel3.experimental.Analog` ports generate error using ChiselSim

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

Having a simple module containing any `Analog` port, generates an error when testing with ChiselSim.

**What is the current behavior?**

A module like:

```scala
class Toplevel() extends Module {
val io = IO(new Bundle {
val in = Input(Bool())
val out = Output(Bool())
val reg = Output(UInt(8.W))
})

val internalReg = RegInit(123.U(8.W))
val dataIn = io.in
io.out := dataIn
io.reg := internalReg
}
```

Prints the error below when testing with ChiselSim (not testing the Analog port per-se).

```
ToplevelSpec:
Toplevel io sample
- should have the output equal to input *** FAILED ***
java.lang.Exception: ls . | grep -v Makefile | grep -v execution-script.txt | xargs rm -rf
\
/opt/homebrew/bin/verilator \
'--cc' \
'--exe' \
'--build' \
'-o' \
'../simulation' \
'--top-module' \
'svsimTestbench' \
'--Mdir' \
'verilated-sources' \
'--assert' \
'-CFLAGS' \
'-std=c++14 -I/private/var/folders/hq/v9yxq5cx53nb9gn_hvspmbm80000gn/T/chisel3.simulator.EphemeralSimulator_84439@cdepaula-mac_13455796989150285355/workdir-default -DSVSIM_ENABLE_VERILATOR_SUPPORT' \
'../primary-sources/Toplevel.sv' 'testbench.sv' '../generated-sources/c-dpi-bridge.cpp' '../generated-sources/simulation-driver.cpp'
%Warning-PINMISSING: testbench.sv:8:10: Cell has missing pin: 'io_analog'
8 | Toplevel dut (
| ^~~
... For warning description see https://verilator.org/warn/PINMISSING?v=5.024
... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)
make: *** [simulation] Error 1
at svsim.Workspace.compile(Workspace.scala:390)
at chisel3.simulator.Simulator$WorkspaceCompiler.liftedTree1$1(Simulator.scala:60)
at chisel3.simulator.Simulator$WorkspaceCompiler.process(Simulator.scala:53)
at chisel3.simulator.SingleBackendSimulator.processBackends(Simulator.scala:139)
at chisel3.simulator.SingleBackendSimulator.processBackends$(Simulator.scala:138)
at chisel3.simulator.EphemeralSimulator$DefaultSimulator.processBackends(EphemeralSimulator.scala:28)
at chisel3.simulator.Simulator._simulate(Simulator.scala:116)
at chisel3.simulator.Simulator._simulate$(Simulator.scala:97)
at chisel3.simulator.EphemeralSimulator$DefaultSimulator._simulate(EphemeralSimulator.scala:28)
at chisel3.simulator.SingleBackendSimulator.simulate(Simulator.scala:146)
...
Run completed in 1 second, 302 milliseconds.
Total number of tests run: 1
Suites: completed 1, aborted 0
Tests: succeeded 0, failed 1, canceled 0, ignored 0, pending 0
*** 1 TEST FAILED ***
1 targets failed
toplevel.test.test 1 tests failed:
ToplevelSpec Toplevel io sample should have the output equal to input
```

**What is the expected behavior?**

Test to succeed without errors.

**Please tell us about your environment:**

Happens on Chisel 6.4.0

❯ verilator --version
Verilator 5.024 2024-04-05 rev UNKNOWN.REV
I'm on MacOS Sonoma 14.5

Reproduce the ChiselSim test using the Toplevel module with an Analog port, then inspect the generated testbench.sv and Toplevel.sv alongside svsim.Workspace.compile in Workspace.scala. The fix is complete when Verilator no longer reports a missing io_analog pin and the test succeeds.

Written by the indexing model from the issue text.