It would be nice if ProbeValues of Literals would automatically expand widths

**Type of issue**: Feature Request

**Is your feature request related to a problem? Please describe.**

Consider the following Chisel:
```scala
val out = IO(Output(Probe(UInt(8.W))))
define(out, ProbeValue(8.U))
```

**Describe the solution you'd like**

This currently errors because the width of `8.U` defaults to 4-bits. While for ProbeValues of normal hardware components like wires, ports, and registers, the widths obviously need to match since Probes are effectively pointers to the specific underlying hardware, literals do not actually correspond to any specific hardware so Chisel is free to pad them as necessary.

This would probably require a change to how `ProbeValue` is implemented--it would need to not eagerly emit a wire but rather delay emitting a Wire until the `define` when it knows the desired width.

**Describe alternatives you've considered**

It's not terrible for the user to have to cast or pad, the mechanical solution here of just writing the following works:
```scala
define(out, ProbeValue(8.U.asTypeOf(out))
```
(Well it will work once https://github.com/chipsalliance/chisel/pull/4168 is merged), but obviously it would be more ergonomic if that weren't necessary.

**Additional context**
Include detailed explanation, stacktraces, related issues, suggestions how to fix, links for us to have context, eg. Stack Overflow, gitter, [Scastie](https://scastie.scala-lang.org/KtzZQ3nFTea9KoNh0tRqtg).

**What is the use case for implementing this feature?**