Source line + carat for errors should work for Scala CLI Example

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

Consider the following example built from the Scala CLI template `chisel-example.scala`:
```scala
//> using scala "2.13.12"
//> using dep "org.chipsalliance::chisel:6.4.0"
//> using plugin "org.chipsalliance:::chisel-plugin:6.4.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.probe._
// _root_ disambiguates from package chisel3.util.circt if user imports chisel3.util._
import _root_.circt.stage.ChiselStage

class Foo extends Module {
val out = IO(Output(Probe(UInt(8.W))))

val w = Wire(UInt(8.W))
define(out, w)

}

object Main extends App {
println(
ChiselStage.emitSystemVerilog(
gen = new Foo,
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)
)
}
```

**What is the current behavior?**

This prints the following error:
```
[error] Users/koenig/work/t/define/chisel-example.scala 15:9: Expected source to be a probe expression.
[error] There were 1 error(s) during hardware elaboration.
Exception in thread "main" chisel3.internal.Errors: Fatal errors during hardware elaboration. Look above for error list. Rerun with --throw-on-first-error if you wish to see a stack trace.
```

**What is the expected behavior?**

If you emit CHIRRTL from a working build, you'll see that when using Scala-CLI, the source locators are absolute but missing the root `/`, e.g.:
```firrtl
input clock : Clock @[Users/koenig/work/t/define/chisel-example.scala 11:7]
```

It seems that Scala-CLI compiles in the root directory but then runs in `.`. The leading `/` is stripped here: https://github.com/chipsalliance/chisel/blob/6c708b19f8407f531c47f9b4d37a2db5327fe677/core/src/main/scala/chisel3/internal/SourceInfoFileResolver.scala#L22
I'm not sure why we're stripping it, but I think we can stop doing that and this will work.

**Please tell us about your environment:**

**Other Information**

**What is the use case for changing the behavior?**

Start in core/src/main/scala/chisel3/internal/SourceInfoFileResolver.scala, especially the path handling at the linked line. Reproduce the Scala CLI chisel-example.scala case and inspect the emitted CHIRRTL source locator. Done means the leading root is preserved and the elaboration error reports the correct source line and caret.

Written by the indexing model from the issue text.