Boring to a FlatIO Port does not properly terminate at the port -- descends into the module

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**
See unit tests added in https://github.com/chipsalliance/chisel/pull/4154

**What is the current behavior?**

Boring to a Module with a FlatIO does not properly terminate at the ports within Aggregates in the FlatIO.
It does work if it is not an Aggregate (if it is an element).

For Ext modules this leads to an annoying error message with a class cast exception because we've descended into the ExtModule which is not very friendly:
https://github.com/chipsalliance/chisel/blob/main/src/main/scala/chisel3/util/experimental/BoringUtils.scala#L273-L281

**What is the expected behavior?**

When boring to an output port on an ExtModule if it is a property, it should bore to the IO and not try to descent into the Module.

Also, if I do hit this scenario for an ExtModule i should get a better error than the class cast exception from
https://github.com/chipsalliance/chisel/blob/main/src/main/scala/chisel3/util/experimental/BoringUtils.scala#L273-L281

**Please tell us about your environment:**

**Other Information**

**What is the use case for changing the behavior?**