provide an Chisel Native API for SystemVerilog bind

**Type of issue**: Feature Request

For a `FixedIOModule`, the `ioGenerator` is its header.

Think about this scenario, Different teams can only access the header for different purpose, e.g. RTL designer, DV engineer seeing `Probe` and `ProbeRW`, Performance Model engineer writing necessary `printf` to specific signals(`Probe` it).

There will be three different end users to the specified `ioGenerator`, and three layers of IO in three colors. three teams are developing three Modules but bind at last.

Currently `bind` can be automatically extracted in CIRCT.

But we may need a way to expose this functionality in Chisel.

Start by reading the FixedIOModule and ioGenerator concepts, then trace how CIRCT currently extracts SystemVerilog bind constructs. The issue does not name files or tests, so first clarify the intended Chisel-native API, its supported users and IO layers, and the acceptance criteria for exposing bind functionality.

Written by the indexing model from the issue text.