How to generate "only" verilog file when useing emitVerilog api

Hi,Sorry for a dummy question , how can I translate my Chisel(3.6.0) codes to only verilog files without systemverilog files when useing emitVerilog!!
thanks a lot!!

Start with the Chisel 3.6.0 emitVerilog API documentation or source to determine whether it supports generating only Verilog files. Done means providing a clear usage example or documenting the limitation and available alternative.

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