We need a getting started documentation

Surfing around at the new website I am missing a plain and hopefully simple Getting Started. The Jupiter thing is nice, but a bit slow and also detached from real HW design work. I think we need a super simple example that can be tested (with chiseltest or something new) and generated to Verilog to explore it in an FPGA.

I’d be happy to contribute on this. We just need to agree where to put it (code and document).

Cheers,
Martin

No files, tests, or entry points are named. Start by locating the website documentation and existing Chisel examples, then review how chiseltest, Verilog generation, and FPGA-oriented workflows are currently demonstrated. Done means a simple Getting Started example is documented, testable, and can be generated to Verilog.

Written by the indexing model from the issue text.