chipsalliance / chipsalliance/chisel

Differences Between := and :<*= involving Analog and DontCare

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Dominant language
Scala
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Description

I've noticed that driving an `Analog` with a `DontCare` in different ways results in differences in whether the analog can be later attached.

Basically, this is an error:

``` scala
b :<= DontCare
b :<= a
```

Whereas this is not an error:

``` scala
b := DontCare
b :<= a
```

The latter produces the following FIRRTL (which should probably elide the invalidate), but compiles:

```
invalidate b
attach (b, a)
```

Full example for playing around with:

``` scala
//> using scala "2.13.11"
//> using repository sonatype-s01:snapshots
//> using lib "org.chipsalliance::chisel::6.0.0-M3+117-2372b1c4-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin::6.0.0-M3+117-2372b1c4-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.experimental.Analog
import circt.stage.ChiselStage

class Foo extends Module {
val a = IO(Analog(1.W))
val b = IO(Analog(1.W))
val c = IO(Analog(1.W))

b := DontCare
b :<= a

c :<= DontCare
c :<= a
}

object Main extends App {
println(
ChiselStage.emitCHIRRTL(
gen = new Foo
)
)
println(
ChiselStage.emitSystemVerilog(
gen = new Foo,
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)
)
}
```

This produces the following error:

```
[error] AnalogConnect.scala 22:5: : Analog Foo.c: IO[Analog<1>] previously bulk to DontCare() is connected to Foo.a: IO[Analog<1>] at @[AnalogConnect.scala 21:5]
[error] There were 1 error(s) during hardware elaboration.
Exception in thread "main" chisel3.internal.Errors: Fatal errors during hardware elaboration. Look above for error list. Rerun with --throw-on-first-error if you wish to see a stack trace.
```

Contributor guide

Open the contributing guide

Research direction

Start with the supplied Foo example and compare ChiselStage.emitCHIRRTL and emitSystemVerilog output for := and :<= with Analog and DontCare. Trace the AnalogConnect.scala diagnostic reported for the :<= case, then identify how the two connection forms record DontCare and later attachment. Done means the behavior is consistent and the resulting FIRRTL does not retain an invalid invalidate/attach combination.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
compilers
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
38/100

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