Reject Input Probes on BlackBox/ExtModule

Input probes on externally defined FIRRTL modules are illegal. Currently, Chisel will create these and lead let FIRRTL error on it. Chisel should error immediately if a user tries to do this.

All of the following ports should be errors:

```scala
//> using scala "2.13.11"
//> using repository sonatype-s01:snapshots
//> using lib "org.chipsalliance::chisel::6.0.0-M3+117-2372b1c4-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin::6.0.0-M3+117-2372b1c4-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.experimental.ExtModule
import chisel3.probe.Probe
import circt.stage.ChiselStage

class Bar extends ExtModule {
val a = IO(Flipped(Probe(Bool())))
val b = IO(Flipped(new Bundle {
val a = Probe(Bool())
}))
val c = IO(new Bundle {
val a = Flipped(Probe(Bool()))
})
val d = IO(Flipped(Vec(1, Probe(Bool()))))
}

class Foo extends Module {
val bar = Module(new Bar)
}

object Main extends App {
println(
ChiselStage.emitSystemVerilog(
gen = new Foo,
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)
)
}
```

Related to improving these errors on the CIRCT side if they do show up: https://github.com/llvm/circt/issues/6432