Naming Plugin Mixup for suggestName, but no val

Bit of a weird one. Consider the following:

```
//> using scala "2.13.11"
//> using repository sonatype-s01:snapshots
//> using lib "org.chipsalliance::chisel::6.0.0-M3+117-2372b1c4-SNAPSHOT"
//> using plugin "org.chipsalliance:::chisel-plugin::6.0.0-M3+117-2372b1c4-SNAPSHOT"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import circt.stage.ChiselStage

class Foo extends RawModule {
IO(Output(Bool())).suggestName("a") :<= IO(Input(Bool())).suggestName("b")
}

object Main extends App {
println(
ChiselStage.emitCHIRRTL(
new Foo
)
)
}
```

This produces a port name for the input of `a_b`. I would have thought this was just `b`:

```
FIRRTL version 3.3.0
circuit Foo :
module Foo :
output a : UInt<1>
input a_b : UInt<1>

connect a, a_b
```

Start by running the Scala example from the issue with the shown Chisel and chisel-plugin snapshot versions, then inspect how suggestName handles the two connected IOs. The fix should prevent the input from inheriting the output's name prefix, producing an input named b rather than a_b, with regression coverage for this example.

Written by the indexing model from the issue text.