Make Chisel5 generate parameter in Verilog

**Type of issue**: Feature Request

**Is your feature request related to a problem? Please describe.**
I think that it will be greater if chisel5 can add parameter function.
In Verilog, it can define parameter in Module.
In Chisel, can we still generate parameters in Module?

**Describe the solution you'd like**
Since Chisel5 has changed its firrtl compiler from SFC to MFC, I think adding parameter function would make Chisel5 even more powerful.

**What is the use case for implementing this feature?**
Consider this condition in which we can only add a parameter file in Verilog with statement `include.
As a result, we do not need to re-run Chisel5 to generate Verilog if we only change the value of parameter in Chisel5.
I think this will be a great benefit to save the time when we use Chisel5 to generate Verilog.

Please consider this suggestion carefully.
Best Regards