Error during Verilog generation (firtool pass) for an SInt-based Queue

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

Create an `SInt`-based `Queue` and try to generate Verilog code for it using `firtool`.

**What is the current behavior?**

For an `SInt`-based [Queue](https://github.com/chipsalliance/chisel/blob/main/src/main/scala/chisel3/util/Decoupled.scala#L244) Verilog generation fails with the following error:
```scala
Decoupled.scala:274:95: error: memories should be flattened before running LowerMemory
Decoupled.scala:274:95: note: see current operation: %5:2 = "firrtl.mem"() {annotations = [], depth = 1024 : i64, name = "ram", nameKind = #firrtl, portAnnotations = [[], []], portNames = ["MPORT", "io_deq_bits_MPORT"], readLatency = 0 : i32, ruw = 0 : i32, writeLatency = 1 : i32} : () -> (!firrtl.bundle, en: uint<1>, clk: clock, data: sint<16>, mask: uint<1>>, !firrtl.bundle, en: uint<1>, clk: clock, data flip: sint<16>>)
```

**What is the expected behavior?**

Generates Verilog just like for any `UInt`-based [Queue](https://github.com/chipsalliance/chisel/blob/main/src/main/scala/chisel3/util/Decoupled.scala#L329) for which it works without any problems.

**Please tell us about your environment:**

Tried with Chisel [v3.6.0](https://github.com/chipsalliance/chisel/releases/tag/v3.6.0) and `firtool` [v1.37.0](https://github.com/llvm/circt/releases/tag/firtool-1.37.0)
OS: Any Linux

**Other Information**

This bug was originally discovered using [Chipyard](https://github.com/ucb-bar/chipyard) where it has also been reported ucb-bar/chipyard#1565

Please see [this](https://github.com/milovanovic/QueueDemo) example for a convenient way and more details on how to reproduce the error. A fairly trivial Scala code containing Queue object instantiation which fails can be found [here](https://github.com/milovanovic/QueueDemo/blob/main/src/main/scala/QueueExample.scala).