`Mem` mistakenly misses mask ports in some cases

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**
``` scala
class Storage extends Bundle {
val s1 = UInt(2.W)
val s2 = Bool()
}

class our extends Module {
val io = IO(new Bundle {
val addr = Input(UInt(3.W))
val wen = Input(Bool())
val wdata = Input(new Storage)
val wenS1 = Input(Bool())
val wdataS1 = Input(UInt(2.W))
val rdata = Output(new Storage)
})

val data = Mem(8, new Storage)
when(io.wenS1) {
data(io.addr).s1 := io.wdataS1
}
when(io.wen) {
data(io.addr) := io.wdata
}

io.rdata := data(io.addr)
}
```
**What is the current behavior?**
It generates something like:
``` verilog
module our(
input clock,
reset,
input [2:0] io_addr, // src/main/scala/gcd/GCD.scala:18:14
input io_wen, // src/main/scala/gcd/GCD.scala:18:14
input [1:0] io_wdata_s1, // src/main/scala/gcd/GCD.scala:18:14
input io_wdata_s2, // src/main/scala/gcd/GCD.scala:18:14
io_wenS1, // src/main/scala/gcd/GCD.scala:18:14
input [1:0] io_wdataS1, // src/main/scala/gcd/GCD.scala:18:14
output [1:0] io_rdata_s1, // src/main/scala/gcd/GCD.scala:18:14
output io_rdata_s2 // src/main/scala/gcd/GCD.scala:18:14
);

wire [2:0] _data_ext_R0_data; // src/main/scala/gcd/GCD.scala:27:17
data_8x3 data_ext ( // src/main/scala/gcd/GCD.scala:27:17
.R0_addr (io_addr),
.R0_en (1'h1),
.R0_clk (clock),
.W0_addr (io_addr),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data ({io_wdata_s2, io_wdata_s1}), // src/main/scala/gcd/GCD.scala:27:17
.W1_addr (io_addr),
.W1_en (io_wenS1),
.W1_clk (clock),
.W1_data ({1'h0, io_wdataS1}), // src/main/scala/gcd/GCD.scala:27:17
.R0_data (_data_ext_R0_data)
);
assign io_rdata_s1 = _data_ext_R0_data[1:0]; // src/main/scala/gcd/GCD.scala:27:17
assign io_rdata_s2 = _data_ext_R0_data[2]; // src/main/scala/gcd/GCD.scala:27:17
endmodule
```

**What is the expected behavior?**
Write masks are expected to be generated.

**Please tell us about your environment:**

- version: 6.0.0-M3
- OS: Linux xxx 5.15.0-69-generic #76~20.04.1-Ubuntu SMP Mon Mar 20 15:54:19 UTC 2023 x86_64 x86_64 x86_64 GNU/Linux
**Other Information**

**What is the use case for changing the behavior?**