Properties in ExtModule/BlackBox are silently dropped

Properties in an `ExtModule` are not emitted to CHIRRTL. Consider the following:

```scala
//> using scala "2.13.11"
//> using lib "org.chipsalliance::chisel::6.0.0-M3"
//> using plugin "org.chipsalliance:::chisel-plugin::6.0.0-M3"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.experimental.ExtModule
import chisel3.properties.Property
import circt.stage.ChiselStage

class Bar extends ExtModule {
val a = IO(Output(Property[Int]()))
}

class Foo extends RawModule {
val a = IO(Output(Property[Int]()))

val bar = Module(new Bar)
a := bar.a
}

object Main extends App {
println(
ChiselStage.emitCHIRRTL(new Foo)
)
println(
ChiselStage.emitSystemVerilog(
gen = new Foo,
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)
)
}
```

This produces the following CHIRRTL:

```
FIRRTL version 3.1.0
circuit Foo :
extmodule Bar :
defname = Bar

module Foo :
output a : Integer

inst bar of Bar
propassign a, bar.a
```

This is illegal and `firtool` complains:

```
Exception in thread "main" circt.stage.phases.Exceptions$FirtoolNonZeroExitCode: firtool returned a non-zero exit code. Note that this version of Chisel (6.0.0-M3) was published against firtool version 1.52.0.
------------------------------------------------------------------------------
ExitCode:
1
STDOUT:

STDERR:
:10:19: error: use of invalid field name 'a' on bundle value
propassign a, bar.a @[Users/schuylereldridge/repos/github.com/seldridge/scala-snippets/PropertiesExtModule.scala 19:5]
```

The same issue exists for `BlackBox`:

```
//> using scala "2.13.11"
//> using lib "org.chipsalliance::chisel::6.0.0-M3"
//> using plugin "org.chipsalliance:::chisel-plugin::6.0.0-M3"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import chisel3.properties.Property
import circt.stage.ChiselStage

class Bar extends BlackBox {
val io = IO(Output(new Bundle {
val a = Property[Int]()
}))
}

class Foo extends RawModule {
val a = IO(Output(Property[Int]()))

val bar = Module(new Bar)
}

object Main extends App {
println(
ChiselStage.emitCHIRRTL(new Foo)
)
}
```

Produces:
```
FIRRTL version 3.1.0
circuit Foo :
extmodule Bar :
defname = Bar

module Foo :
output a : Integer

inst bar of Bar
```