error: value is not a member of chisel3.Bundle

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

1. config for build.sbt
```scala
// build.sbt
scalaVersion := "2.13.7"
addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "3.5.0-RC2" cross CrossVersion.full)
libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.5.0-RC2"
// We also recommend using chiseltest for writing unit tests
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.5.0-RC2" % "test"
```
2. chisel code
```scala
import chisel3._
import chisel3.stage.ChiselStage

object Hello extends App {
new ChiselStage().emitVerilog(new TopModule(), Array("-td", "chisel"))
}

class TopModule extends BaseCell {
val io = IO(new BaseCellIO {
val out: UInt = Output(UInt(1.W))
})
io.out := 1.U
}

trait BaseCellIO extends Bundle {
val out: UInt
}

abstract class BaseCell extends RawModule {
val io: BaseCellIO
}
```
3. `sbt compile` or run the module by hello will report error.

**What is the current behavior?**
report the error info:
```
value out is not a member of chisel3.Bundle with BaseCellIO
did you mean out?
io.out := 1.U
```
**What is the expected behavior?**
compile or run successfully.

**Please tell us about your environment:**
- scalaVersion: `2.13.7`
- OS: `Windows 10 家庭中文版`
- jdk: `1.8.0_251`
- sbt: `1.3.8`

**Other Information**

**What is the use case for changing the behavior?**

Start with the build.sbt configuration and the minimal Hello, TopModule, BaseCellIO, and BaseCell example, then reproduce the failure with sbt compile or by running Hello. Trace why io.out is rejected for the BaseCellIO type, and consider the issue done when the example compiles and emitVerilog runs successfully.

Written by the indexing model from the issue text.