Vector slice reference error

**Type of issue:** bug report

**Impact:** Trait variables not being referenced

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

I have a trait `Config` defined as follows

```scala
package configs

trait Configs {
val XLEN : Int = 32
val ByteWidth : Int = 8
val HalfWordWidth: Int = 16
val RegAddrWidth : Int = 5
val OpcodeWidth : Int = 7
val Funct3Width : Int = 3
val Funct7Width : Int = 7

val WMaskWidth: Int = 4
val AddrWidth : Int = 8
}
```

The module that I am importing this trait is as follows

```scala
package core.execute_stage

import chisel3._,
chisel3.util._
import configs.Configs,
core.decode_stage.DMemCtrl,
core.pipeline_regs.RegDEIO

class DMemAlignerIO extends Bundle with Configs {
val alu : SInt = Flipped(new ALUIO().out)
val ctrl: DMemCtrl = Flipped(new RegDEIO().dMemCtrl)
val data: SInt = Flipped(new RegDEIO().intData(1))
}

class DMemAligner extends Module with Configs {
val io: DMemAlignerIO = IO(new DMemAlignerIO)

val offset: UInt = io.alu(1, 0)
val addr : UInt = io.alu(AddrWidth + 1, 2)
val align : Bool = RegInit(0.B)

val byte : UInt = WireInit(io.data(ByteWidth - 1, 0))
val halfWord: UInt = WireInit(io.data(HalfWordWidth - 1, 0))
}
```

**What is the current behavior?**

On compiling with sbt, I am receiving the following error

```sbt
chisel3.package$ChiselException: Internal Error! Could not get ref for 'SInt<32>[3]' @[src/main/scala/core/execute_stage/DMemAligner.scala 24:40]! 'SInt<32>[3]' was defined in module 'core.execute_stage.DMemAligner@5a765e3c'. This is a bug in Chisel, please file an issue at 'https://github.com/chipsalliance/chisel3/issues/new'
[info] at chisel3.internal.throwException$.apply(Error.scala:93)
[info] at chisel3.internal.firrtl.Converter$.reportInternalError(Converter.scala:33)
[info] at chisel3.internal.firrtl.Converter$.$anonfun$getRef$1(Converter.scala:40)
[info] at scala.Option.getOrElse(Option.scala:201)
[info] at chisel3.internal.firrtl.Converter$.getRef(Converter.scala:37)
[info] at chisel3.internal.firrtl.Converter$.convert(Converter.scala:67)
[info] at chisel3.internal.firrtl.Converter$.convert(Converter.scala:75)
[info] at chisel3.internal.firrtl.Converter$.$anonfun$convertSimpleCommand$1(Converter.scala:116)
[info] at scala.collection.StrictOptimizedIterableOps.flatMap(StrictOptimizedIterableOps.scala:118)
[info] at scala.collection.StrictOptimizedIterableOps.flatMap$(StrictOptimizedIterableOps.scala:105)
[info] ...
```

Tracking the problem, I found that the variable `ByteWidth` is not being referenced (and also suspect that `HalfWordWidth` will also not be referenced), though I have already inherited the trait `Config` in the class definition.

**What is the expected behavior?**

The trait values should be called

**Please tell us about your environment:**

sbt version = 1.7.1
chisel version = 3.6.0
scala version = 2.13.10