chipsalliance / chipsalliance/chisel

How about multi-thread elaboration of modules?

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Dominant language
Scala
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Description

**Type of issue**: Feature Request

**Is your feature request related to a problem? Please describe.**
Not a problem. But it is slow for Chisel elaborate a large design.

**Describe the solution you'd like**
Ideally, modules are independent to each others when clearly declaring the IOs. So it might speed up the elaboration time when each independent module occupies one thread.

**Describe alternatives you've considered**
If we design each Module seperately like Verilog, and each sub module with a placeholder or a blackbox, we can still elaborate each module in different process or thread. But that would decrease the flexibility of Chisel.

**Additional context**
NA.

**What is the use case for implementing this feature?**
If with multi-thread, it could be possible to reduce the Chisel elaboration time significantly.

Contributor guide

Open the contributing guide

Research direction

The issue names no files, tests, or entry points. Start by tracing Chisel's module elaboration path and identify how independent modules are currently discovered and processed. Done would require a concrete concurrency design, validation of preserved elaboration behavior, and measurements showing whether large designs elaborate faster.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
compilers, performance
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
20/100

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