MixedVecInit should handle signals with bi-directions like VecInit

**Type of issue**: Feature Request (It is also a bug report)

**Is your feature request related to a problem? Please describe.**

If I use `MixedVecInit` with multiple bidirectional bundles such as `DecoupledIO`, it will erase the original directions, and cause bugs.

```scala
val a1 = IO(Decoupled(UInt(2.W)))
val b2 = IO(Decoupled(UInt(2.W)))
val m1 = MixedVecInit(a1, b2) // bugs
val m2 = VecInit(a1, b2) // correct
```

In `MixedVecInit.apply(elt)`, chisel developers just use `a := b` to assign signals. So if `elt` is a Bundle with both `Input` and `Output` directions, some signals won't be connected correctly.

**Describe the solution you'd like**
A clear and concise description of what you want to happen.

`MixedVecInit.apply(..)` should have a similar implementation like `VecInit` (see the following figure).

**Describe alternatives you've considered**
A clear and concise description of any alternative solutions or features you've considered.

**Additional context**
Include detailed explanation, stacktraces, related issues, suggestions how to fix, links for us to have context, eg. Stack Overflow, gitter, [Scastie](https://scastie.scala-lang.org/KtzZQ3nFTea9KoNh0tRqtg).

**What is the use case for implementing this feature?**

Included in the above code snippet.

Start at MixedVecInit.apply and compare its assignment behavior with VecInit, as suggested by the issue. Reproduce the DecoupledIO example and trace how bidirectional bundle directions are handled. Done means MixedVecInit preserves those directions like VecInit, with regression coverage for the reported case.

Written by the indexing model from the issue text.