Don't duplicate code if tapping/boring the same thing twice

**Type of issue**: Feature Request

**Is your feature request related to a problem? Please describe.**
Currently the boring will generate duplicate wires if the same hardware thing is tapped/bored. E.g. for this test in `BoringUtilsSpec.scala`:

```scala
new RawModule {
class Foo() extends RawModule {
val internalWire = Wire(Bool())
}

val foo = Module(new Foo())
val outProbe = IO(probe.Probe(Bool()))
val out = IO(Bool())

probe.define(outProbe, BoringUtils.tap(foo.internalWire))

out := BoringUtils.tapAndRead(foo.internalWire)
}
```

The following FIRRTL is generated
```
circuit BoringUtilsSpec_Anon :
module Foo :
output bore : Probe>
output out_bore : Probe>

wire internalWire : UInt<1>
define bore = probe(internalWire)
define out_bore = probe(internalWire)

module BoringUtilsSpec_Anon :
output outProbe : Probe>
output out : UInt<1>

inst foo of Foo
define outProbe = foo.bore
out <= read(foo.out_bore)
```
However, the second bore is unnecessary.

**Describe the solution you'd like**
The above could instead be emitted as:

```
circuit BoringUtilsSpec_Anon :
module Foo :
output bore : Probe>

wire internalWire : UInt<1>
define bore = probe(internalWire)

module BoringUtilsSpec_Anon :
output outProbe : Probe>
output out : UInt<1>

inst foo of Foo
define outProbe = foo.bore
out <= read(foo.bore)
```

**Describe alternatives you've considered**
None

**Additional context**
https://github.com/chipsalliance/chisel/pull/3237

**What is the use case for implementing this feature?**
This affects any code that taps or bores the same signal more than once.