chipsalliance / chipsalliance/chisel
Adding a flag to `circt.stage.ChiselStage.emitFIRRTL` which presents the pre-optimized FIRRTL rather than the (post-) optimized FIRRTL
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- Scala
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Description
**Type of issue**: Feature Request
**Is your feature request related to a problem? Please describe.**
I would like a way to inspect the FIRRTL output of my Chisel program's execution to verify it is working the way I am intending it to.
In particular, I would like to see the FIRRTL as it is presented to the CIRCT optimizer rather than the resulting FIRRTL that comes out at the end of the optimizer.
I know that the `emitCHIRRTL` method provides something very close to this -- and for the time being, that is a viable workaround. However, it seems that "CHIRRTL" is an informal extension of FIRRTL. It is arguably an implementation detail that has leaked into the public API.
I would like the guarantee that the output is valid FIRRTL, as per the spec, but before any optimization takes place.
**Describe the solution you'd like**
I think it would be simple to either have an optional `optimize` argument to the `emitFIRRTL` method, eg: `stage.emitFIRRTL(optimize=false)`.
Alternatively, it could be a separate method: `stage.emitUnoptimizedFIRRTL`.
**What is the use case for implementing this feature?**
I want this for pedagogical purposes.
When writing generators in Chisel, you have a lot of power in the kind of hardware you can generate. It is often instructive to inspect the FIRRTL output to get a more concrete idea of what the generator "does". I want to be able to talk about the FIRRTL output of a generator while avoiding:
1. A discussion of what "CHIRRTL" is, and
2. Having to compensate for the optimizer
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