(Optionally?) Add FIRRTL Pretty Printing

For any non-trivial design, the sizes of bundles can get very, very large. This is particularly apparent for modules which use libraries which auto-generate a ton of ports and put them all in the same bundle (i.e., diplomacy). This can create modules like:

```
module Foo:
input clock: Clock
input reset: UInt<1>
input auto: { a: { ... }, b: { ... }, c : { d: { e: ... } } }
```

FIRRTL technically supports line breaks in types. The above could be made much more readable in the FIRRTL output as:

```
module Foo:
input clock: Clock
input reset: UInt<1>
input auto: {
a: { ... },
b: { ... },
c : {
d: {
e: ...
}
}
}
```

Experiment with an option to turn this on and see the effect on the output and the serialization time. (FIRRTL does not have type annotations which means these would only show up on ports, wires, and registers.) See about making this the default. If we do this, enshrine it in the FIRRTL spec as legal.

Start by locating the FIRRTL output and serialization paths, then compare compact and pretty-printed output on designs with deeply nested bundles. Measure serialization time and output readability; done means an optional pretty-printing mode is evaluated, with a default considered and legal line breaks documented in the FIRRTL spec if adopted.

Written by the indexing model from the issue text.