chipsalliance / chipsalliance/chisel
Move Mem integration tests into its own Spec
- Dominant language
- Scala
- Stars
- 4.8k
- Forks
- 658
- Avg merge
- 18h 59m
- Merged PRs (30d)
- 14
Description
Currently, `src/test/scala/chiselTests/Mem.scala` is filled with unit tests which generate and check CHIRRTL and integration tests which compile to Verilog through MFC and run Verilator to perform a multi-cycle test. Ideally, the integration/simulation tests should be moved in their own file to better separate the CHIRRTL-only tests from them.
Contributor guide
Research direction
Start by reading src/test/scala/chiselTests/Mem.scala and identify which tests generate and check CHIRRTL versus those that compile to Verilog through MFC and run Verilator. Move the integration and simulation tests into a separate spec while keeping the CHIRRTL-only tests in Mem.scala, then run the relevant Mem test suite to verify both groups still pass.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- testing
- Issue type
- Refactor
- Difficulty
- 2/5
- Estimated time
- 1-3 hours
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 45/100