chipsalliance / chipsalliance/chisel
Source Locators Are Absolute, but Missing Leading Slash
- Dominant language
- Scala
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Description
I noticed that the firtool-produced error messages coming out of scala-cli are not showing up. I think this is due to the source locators being emitted kind of strangely. Consider:
```scala
//> using scala "2.13.10"
//> using lib "org.chipsalliance::chisel::5.0.0-RC1"
//> using plugin "org.chipsalliance:::chisel-plugin::5.0.0-RC1"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"
import chisel3._
import circt.stage.ChiselStage
class Foo extends Module {
val x = IO(Output(Reset()))
}
object Main extends App {
println(ChiselStage.emitCHIRRTL(new Foo))
println(
ChiselStage.emitSystemVerilog(
gen = new Foo,
firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
)
)
}
```
The CHIRRTL is:
```
FIRRTL version 2.0.0
circuit Foo :
module Foo :
input clock : Clock
input reset : UInt<1>
output x : Reset @[Users/schuylere/repos/github.com/llvm/circt/build/scala-cli/Foo.scala 10:13]
skip
```
Note that the source locator is `Users/schuylere/...`. I.e., this is a relative path, but is actually absolute.
The error (top-level module uninferred reset port) is then reported as:
```
Users/schuylere/repos/github.com/llvm/circt/build/scala-cli/Foo.scala:10:13: error: a port "x" with abstract reset type was unable to be inferred by InferResets (is this a top-level port?)
:3:10: note: the module with this uninferred reset port was defined here
module Foo :
^
```
If I manually change the source locator to be absolute, I get:
```
/Users/schuylere/repos/github.com/llvm/circt/build/scala-cli/Foo.scala:10:13: error: a port "x" with abstract reset type was unable to be inferred by InferResets (is this a top-level port?)
val x = IO(Output(Reset()))
^
Foo.fir:3:10: note: the module with this uninferred reset port was defined here
module Foo :
^
```
Contributor guide
Research direction
Reproduce the scala-cli example using ChiselStage.emitCHIRRTL or emitSystemVerilog and inspect how the source locator reaches firtool. Compare the emitted locator with firtool's diagnostic output; done means absolute source paths include their leading slash and diagnostics still point to the source line.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 48/100