Output bundle can't be assigned Mux

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

```scala
import chisel3._
import chisel3.util._

class Top extends RawModule {
val q = IO(Output(Vec(2, Bool())))

val a = WireInit(VecInit(1.B, 0.B))
val b = WireInit(VecInit(0.B, 1.B))

q <> Mux(1.B, a, b)
}

object Main extends App {
(new chisel3.stage.ChiselStage)
.emitVerilog(new Top, args)
}
```

**What is the current behavior?**

```
chisel3.internal.ChiselException: internal error: attempted to generate LHS ref to ReadOnlyBinding OpBinding(Top@248deced,None)
```

**What is the expected behavior?**

It shouldn't error.

**Please tell us about your environment:**

- version: `3.6-SNAPSHOT`

**Other Information**

**What is the use case for changing the behavior?**