Bad error message from unsanitary port names

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

Name a port with characters that are not legal Verilog and you'll get this error, see the following Scastie:
https://scastie.scala-lang.org/mHRyrwNCScCZIfElmoX8nQ

```scala
import chisel3._

class Example extends Module {
val foo, bar = IO(Input(UInt(8.W)))
val out = IO(Output(UInt(8.W)))

// Add a character to the name that will be sanitized away
out.suggestName("out-")

out := foo + bar
}
```

**What is the current behavior?**

You'll get this error:
```
[error] DeletedWrapper.scala:38: Cannot have duplicate names out and out-
[error] There were 1 error(s) during hardware elaboration.
```

**What is the expected behavior?**

I'm not sure if this should be an error or not, but at the very least, the error message should be more precise. Also ideally, if it is an error, it should give some source locator or stack trace. Note that this works with Chisel 3.5.5 and just drops the unsanitary characters: https://scastie.scala-lang.org/hJ1sDILoT3aHO0RjyehdEg

**Please tell us about your environment:**

**Other Information**

**What is the use case for changing the behavior?**

Start with the linked Scastie reproduction and trace the hardware elaboration path for the suggested port name "out-". Determine whether sanitized-name collisions should be rejected or normalized, then define the expected diagnostic, including any source location or stack trace, and cover the chosen behavior with a regression test.

Written by the indexing model from the issue text.