DontCare in Mux should remove mux logic

**Type of issue**: Feature Request

**Is your feature request related to a problem? Please describe.**
Sometimes I have a DontCare show up in a mux like so:
```
m := Mux(sel, a, DontCare)
```
Currently, this emits Verilog like this:
```
assign m = sel ? a : 8'h0;
```
However, the evaluation of `sel` could have been optimized out, and that is no longer possible with this Verilog. Since the third argument of the mux is a DontCare, and not actually a 0, this could have been written:
```
assign m = a;
```
This optimizes out the evaluation of `sel` and the mux, and it does not force `m` to 0 when it doesn't have to.

**Describe the solution you'd like**
When one of the data arguments of a Mux is DontCare, the expression should trivialize to the other data argument.
```
Mux(sel, a, DontCare) -> a
Mux(sel, DontCare, b) -> b
Mux(sel, DontCare, DontCare) -> DontCare
```

**Additional context**
Here is a demonstration in Scastie: https://scastie.scala-lang.org/GVHwYBWOS9ek14Y07cXPLA. Of course this is simplified for the sake of demonstration; in reality, the DontCare may appear through some more obscure means.

**What is the use case for implementing this feature?**
This can improve the performance of generated Verilog by removing some unnecessary logic when dealing with DontCare.

Start from the Mux and DontCare entry points in the Scala implementation and use the linked Scastie demonstration to compare the current behavior. Verify the three requested simplifications and confirm that generated Verilog no longer retains unnecessary mux or select logic.

Written by the indexing model from the issue text.