Chisel sometimes emits bulk connects when it should blast the connection apart

**Type of issue**: Bug Report

**Please provide the steps to reproduce the problem:**

```scala
class Example extends Module {
val enq = IO(new Bundle { val x = Flipped(Decoupled(UInt(8.W))) })
val deq = IO(new Bundle { val x = Decoupled(UInt(8.W)) })
val monitor = IO(Output(new Bundle { val x = Decoupled(UInt(8.W)) }))

deq <> enq
monitor := enq

}
```
Scastie: https://scastie.scala-lang.org/zkCtWnbpRVCNOZud6OD9oQ

**What is the current behavior?**

This emits invalid FIRRTL:
```
circuit Example :
module Example :
input clock : Clock
input reset : UInt<1>
output enq : { flip x : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}}
output deq : { x : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}}
output monitor : { x : { ready : UInt<1>, valid : UInt<1>, bits : UInt<8>}}

deq.x <= enq.x
monitor.x <= enq.x
```

**What is the expected behavior?**

The issue is the `monitor.x <= enq.x` connection, the types are not the same (because monitor is coerced), so Chisel should break the connection apart.

Start by running the Scala reproduction in the linked Scastie example and compare its generated FIRRTL with the output shown here. Trace the handling of the coerced monitor connection; done means the generated FIRRTL avoids the invalid bulk connect by splitting the connection into type-compatible parts.

Written by the indexing model from the issue text.