Auto BlackBox

**Type of issue**: Feature Request

**Is your feature request related to a problem? Please describe.**
For each time we use blackbox, we should use `val io`, and guarantee IO is same with `BlackBox`.
However since Verilog can be parsed, we can auto construct the IO via external parser, e.g: slang.

**Describe the solution you'd like**
Here is a snippet I used to auto generate the IO for BlackBox, I was going to PR this, but found I used the 2.13 only syntax ;p
```scala
class AutoBundleFromVerilog(verilog: String) extends Record {
private val verilogAst = {
val file = os.temp()
os.proc(
"slang",
os.temp(verilog),
"--single-unit",
"--ignore-unknown-modules",
"--compat", "vcs",
"--ast-json",
file
).call(stderr = new ProcessOutput {
override def redirectTo: ProcessBuilder.Redirect =
ProcessBuilder.Redirect.DISCARD

override def processOutput(
out: => SubProcess.OutputStream
): Option[Runnable] = None
})
ujson.read(os.read(file))
}

override val elements: SeqMap[String, Data] = scala.collection.immutable.SeqMap.from {
verilogAst.obj("members").arr.flatMap {
case value: ujson.Obj
if value.value("kind").strOpt.contains("Instance") =>
value.value("body").obj.value("members").arr.flatMap {
case value: ujson.Obj
if value.value("kind").strOpt.contains("Port") =>
Some(
value.value("name").str -> {
val width: Int = value.value("type").str match {
case s"logic[${x}:${y}]" => x.toInt - y.toInt + 1
case s"logic" => 1
}
value.value("direction").str match {
case "In" => Input(UInt(width.W))
case "Out" => Output(UInt(width.W))
case "InOut" => Analog(width.W)
}
}
)
case _ => None
}
case _ => None
}
}

override def cloneType: AutoBundleFromVerilog.this.type =
new AutoBundleFromVerilog(verilog).asInstanceOf[this.type]
}

class AutoBlackBoxFromVerilog(verilog: String) extends BlackBox with HasBlackBoxInline {
val io = IO(new AutoBundleFromVerilog(verilog))
setInline(verilog, s"$desiredName.sv")
}
```

**What is the use case for implementing this feature?**
no more user defined IO in blackboxes.

Start by reviewing the existing BlackBox and HasBlackBoxInline APIs, then examine the AutoBundleFromVerilog and AutoBlackBoxFromVerilog entry points shown in the issue. Investigate the slang AST-JSON invocation and the Scala 2.13 syntax dependency. Done should mean BlackBox IO can be derived from the supplied Verilog without user-defined IO.

Written by the indexing model from the issue text.