chipsalliance / chipsalliance/chisel
Cause: chisel3.internal.ChiselException: Error: attempted to instantiate a Module without wrapping it in Module()
- Dominant language
- Scala
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Description
when i just want to use a function of module (test),
when use Module(new test), a verilog module which is not expected is generated,
when use new test, the following error
"Cause: chisel3.internal.ChiselException: Error: attempted to instantiate a Module without wrapping it in Module()"
comes out
any way that can help me use the method of test, but no extra verilog module is generated
Contributor guide
Research direction
Reproduce the reported error using the `Module(new test)` and `new test` forms, then inspect Chisel's Module instantiation rules and related test coverage. Done means determining whether a supported pattern can call the method without generating an extra Verilog module, or documenting that no such pattern exists.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- compilers
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100