chipsalliance / chipsalliance/chisel

Cause: chisel3.internal.ChiselException: Error: attempted to instantiate a Module without wrapping it in Module()

Open
#2,848 4 comments 0 reactions 0 assignees View on GitHub
Dominant language
Scala
Stars
4.8k
Forks
658
Avg merge
18h 59m
Merged PRs (30d)
14

Description

when i just want to use a function of module (test),
when use Module(new test), a verilog module which is not expected is generated,
when use new test, the following error
"Cause: chisel3.internal.ChiselException: Error: attempted to instantiate a Module without wrapping it in Module()"
comes out

any way that can help me use the method of test, but no extra verilog module is generated

Contributor guide

Open the contributing guide

Research direction

Reproduce the reported error using the `Module(new test)` and `new test` forms, then inspect Chisel's Module instantiation rules and related test coverage. Done means determining whether a supported pattern can call the method without generating an extra Verilog module, or documenting that no such pattern exists.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
compilers
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
20/100

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.