Memory issues

**Type of issue**: Bug Report

**Please tell us about your environment:**
- version: `3.5.4`

I am not sure if it is a Chisel or a chiseltest issue. I am having trouble with ```SyncReadMem```. Maybe it is an issue in my code, but I feel totally lost. I tried to minimize the problem as far as possible. It is committed at: https://github.com/schoeberl/chisel-playground and the example can be run with ```sbt "testOnly issues.FifoSpec"```.

The code writes to a 4-entry memory several values into address 0: https://github.com/schoeberl/chisel-playground/blob/6de172cdaa708050a53c797e291737621e7574c9/src/main/scala/issues/MemFifo.scala#L71

However, when it reads out from an (unrelated) address 3 it receives some data: [some](https://github.com/schoeberl/chisel-playground/blob/6de172cdaa708050a53c797e291737621e7574c9/src/main/scala/issues/MemFifo.scala#L72)

This issue is best seen in the VCD waveform, where the memory content is visible with Verilator (as mem[x][15:0]).

Start with the minimized reproduction in issues/MemFifo.scala, especially the writes around line 71 and reads around line 72, then run sbt "testOnly issues.FifoSpec". Inspect the VCD waveform with Verilator and trace the SyncReadMem behavior. Done means identifying whether the unexpected read data comes from Chisel or chiseltest and documenting or fixing the reproducible behavior.

Written by the indexing model from the issue text.