chipsalliance / chipsalliance/chisel
Inconsistent/Misleading error messages for illegal ReferenceTargets
- Dominant language
- Scala
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Description
**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
```
class Bar extends RawModule {
val vec = IO(Input(Vec(3,Bool())))
val lit = 1.U
val notLit = vec(lit)
}
class Foo extends RawModule {
val bar = Module(new Bar)
bar.notLit.toTarget
}
ChiselStage.elaborate(new Foo)
}
```
**What is the current behavior?**
```
Vectors which are indexed by literal values should successfully be converted to Reference Target *** FAILED ***
[info] chisel3.internal.ChiselException: Illegal component name: vec[UInt<1>("h01")] (note: literals are illegal)
[info]
```
**What is the expected behavior?**
I would get a Reference Target attached to the not-literal vector element
**Please tell us about your environment:**
3.5.x
**Other Information**
**What is the use case for changing the behavior?**
wanting to put reference targets on specific vector elements
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Assessment
This issue has not been assessed yet.