metadata for syn and P&R

**Type of issue**: Feature Request

**Is your feature request related to a problem? Please describe.**
The common metadatas for Synthesis and P&R is required for ASIC designs, Chisel doesn't provide a standard library for it, but most of users are using their own helpers to do so, we observe there are APIs in CIRCT, for example,
https://github.com/llvm/circt/blob/539e148b1d0ae0c00cff81d0dbf655c8ad102daa/test/Dialect/FIRRTL/emit-metadata.mlir#L16-L30
and https://github.com/ucb-bar/barstools also provides such behaviors.

**Describe the solution you'd like**
I wonder if we can come up with a helper library for synthesis, floorplan, memory compile, rom compile, etc, to provide a general post-rtl metadata/IR.

**What is the use case for implementing this feature?**
To unify a ASIC implementation metadata for Chisel.

Start by reviewing the linked CIRCT FIRRTL emit-metadata.mlir example and the referenced ucb-bar/barstools behavior to identify the metadata categories they support. The issue needs an agreed scope and API for unified synthesis, floorplan, memory-compile, and ROM-compile metadata before implementation can be considered complete.

Written by the indexing model from the issue text.