chipsalliance / chipsalliance/chisel

Micro-optimization opportunity in Queue

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Scala
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Description

The current logic for updating the `maybe_full` flag in Queue is `when(do_enq =/= do_deq) { maybe_full := do_enq }` (which, incidentally, is the same as `maybe_full := majority(maybe_full, do_enq, !do_deq)`, and indeed, DC synthesizes it that way). However, I'm pretty sure it can be simplified to `maybe_full := do_enq || (mabye_full && !do_deq)`. The proof sketch is that the latter expression differs from the previous ones only when `do_enq` is true, and in such cases it's impossible for the queue to be empty on the following cycle.

The savings is only one AOI gate, but some designs have tons of queues, and if it's free...

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