chipsalliance / chipsalliance/chisel

ROM construct

Open
#266 16 comments 0 reactions 1 assignee Claimed by @azidar View on GitHub
Feature feature request
Dominant language
Scala
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Forks
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Avg merge
18h 59m
Merged PRs (30d)
14

Description

In case anyone has extra time on their hand, there should be a version of ROM similar to smem that a FIRRTL pass can be run on to possibly generate a black box -- some vendors have ROM compilers that would be better to use than nests of combinational logic.

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