Constraint Mux1H to provide deactivated output when given a zero-hot selector.

https://github.com/chipsalliance/chisel3/blob/1c5d1b5317a0c9fe7ef9d15138065a817380a1e4/src/main/scala/chisel3/util/Mux.scala#L24

The [documentation](https://www.chisel-lang.org/chisel3/docs/explanations/muxes-and-input-selection.html#mux1h) for Mux1H says "If zero or multiple selectors are set the behavior is undefined", however, the methodology for implementing 1-hot muxes automatically makes the output all zeros when none of the inputs are selected by the selector bits (aka 0-hot selection). I've tested this with Vec[Bool] and Vec[UInt] and the current code is operating as I described. I propose the documentation support this case officially.