Reflective naming will override the name given by naming plugin

Consider
```scala
class Example extends Module {
val foo, bar = IO(Input(UInt(8.W)))
val out = IO(Output(UInt(8.W)))

val sum = foo + bar
dontTouch(sum)

// Reflection here overwrites the name of sum
val fuzz = sum

out := sum
}
```

If you generate Verilog from this, you will get the following:
```verilog
module Example(
input clock,
input reset,
input [7:0] foo,
input [7:0] bar,
output [7:0] out
);
wire [7:0] fuzz = foo + bar; // @[main.scala 10:17]
assign out = fuzz; // @[main.scala 15:7]
endmodule
```
Scastie: https://scastie.scala-lang.org/RMgRfAfKTpmtAgKOxBxnZQ

Note that this only occurs because `fuzz` is earlier in the alphabet than `sum` and the reflective naming is done in alphabetical order.

I plan to fix this in 3.6 by removing all reflective naming. We could attempt to fix this as a bug fix in a minor version, but because the required change is so intrusive and breaks some [bad & deprecated] APIs, I think it's simplest just to change this on the major version.

**Type of issue**: bug report

**Impact**: API modification | unknown

**Development Phase**: request

**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

**What is the current behavior?**

See above

**What is the expected behavior?**

See above

**Please tell us about your environment:**

**What is the use case for changing the behavior?**

More predictable naming behavior