sub field assignment

As I cannot reopen issue #878, I created a new one. If this is too hard to implement then we can close it again (maybe with an argument).

Subword (individual bit) assignment should be possible in Chisel (like in V*).

I have students stumbled over this several times.

It is a very common pattern in Verilog and VHDL to consider a multi-bit wire or signal just as an indexable collection of bits. Many textbook examples in VHDL and Verilog are written in this style, e.g., the Dally book uses this extensively.

By adding another standard example to my book (simple arbiter), I stumbled again self over this issue. Here is a code example.

```
val grant = WireDefault(0.U(3.W))

grant(0) := request(0)
notGranted(0) := ~grant(0)
grant(1) := request(1) & notGranted(0)
notGranted(1) := ~grant(1) & notGranted(0)
grant(2) := request(2) & notGranted(1)
```

Those are all ```UInt```s. I know that I can work around with ```VecInit(io.request.asBools)``` and ```grant.asUInt```.

Start from the UInt example in the issue and compare the requested direct bit assignments with the stated VecInit(asBools) and asUInt workaround. Determine the existing Chisel behavior for subfield assignment and define completion as supporting the shown grant assignments without that conversion workaround.

Written by the indexing model from the issue text.