chipsalliance / chipsalliance/chisel

Exception in thread "main" firrtl.FirrtlInternalException: No width: UnknownType

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bug
Dominant language
Scala
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Description

bug report

**What is the current behavior?**

```
$ cat input1.firrtl
circuit main :
module main :
node a = dshl(UInt<64>(0), rem(UInt<1>(1), SInt<32>(0)))
```

```
$ java -cp firrtl.jar firrtl.stage.FirrtlMain -o /dev/null -i input1.firrtl 2>&1 | head -1
Exception in thread "main" firrtl.FirrtlInternalException: No width: UnknownType
```

**Please tell us about your environment:**

Using firrtl-1.5.2.

```
$ uname -srio
Linux 4.4.0-31-generic x86_64 GNU/Linux
```

Contributor guide

Open the contributing guide

Research direction

Reproduce the failure with input1.firrtl using the FirrtlMain command shown in the report and firrtl-1.5.2. Trace how the compiler handles dshl and rem when it encounters UnknownType, then verify that the same input no longer terminates with FirrtlInternalException: No width: UnknownType or that it produces an appropriate diagnostic.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
compilers
Issue type
Bug
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
48/100

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