chipsalliance / chipsalliance/chisel
incrementing a register
Open
- Dominant language
- Scala
- Stars
- 4.8k
- Forks
- 658
- Avg merge
- 18h 59m
- Merged PRs (30d)
- 14
Description
**Type of issue**: feature request
**Impact**: API addition (no impact on existing code)
**Development Phase**: proposal
Incrementing a register (a counter) is such a common operation. Maybe we should support an increment operator:
```
cntReg += 1.U
```
Contributor guide
Research direction
No file, test, or entry point is named. Start by reviewing Chisel's register APIs and existing operator-overload handling, then determine the expected semantics for `cntReg += 1.U`. Done means the proposed syntax is supported consistently and covered by tests, but the issue's design proposal needs resolution first.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- compilers, embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 25/100