chipsalliance / chipsalliance/chisel

incrementing a register

Open
#2,464 1 comment 1 reaction 0 assignees View on GitHub
Dominant language
Scala
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Description

**Type of issue**: feature request

**Impact**: API addition (no impact on existing code)

**Development Phase**: proposal

Incrementing a register (a counter) is such a common operation. Maybe we should support an increment operator:
```
cntReg += 1.U
```

Contributor guide

Open the contributing guide

Research direction

No file, test, or entry point is named. Start by reviewing Chisel's register APIs and existing operator-overload handling, then determine the expected semantics for `cntReg += 1.U`. Done means the proposed syntax is supported consistently and covered by tests, but the issue's design proposal needs resolution first.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
compilers, embedded-iot
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
25/100

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