chipsalliance / chipsalliance/chisel
Why Analog() still experimental ?
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Description
Is there a reason why `Analog()` direction port type is still in [experimental module ](https://www.chisel-lang.org/api/latest/chisel3/experimental/Analog.html)?
It has been used for a long time in several project. It's very useful for connecting some 'hard macro' in FPGA.
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