Vec[Bool] is a bad idea

This is an informational post that should probably be made into a documentation page somewhere.

I've found (as have others) that using Vec[Bool] is mostly a bad idea and should only be done sparingly. I have a project written in Chisel that generates network switches. I mostly used Vec[Bool] everywhere just in case I needed to easily be able to modify subset of the bits. After some searching I found this to be a bad idea for many reasons.

I created a 16 port switch where the datapath is 256 bits wide. With everything defined as Vec[Bool], generating the Verilog consumed 22.5GB of memory at took over 8 minutes. The resulting Verilog has 2.3 million lines.

After converting just the major datapaths to UInt the same design only took 3.3GB of memory and 42 seconds the generate. The resulting Verilog has 69k lines.

I think the documentation page for Vec should tell users to only use it when absolutely needed.