chipsalliance / chipsalliance/chisel
Mem issues clock warnings for unclocked ports
- Dominant language
- Scala
- Stars
- 4.8k
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- 18h 59m
- Merged PRs (30d)
- 14
Description
In #2333, we introduced warnings when the implicit clock at Mem declaration time doesn't match the implicit clock at Mem port generation time. These warnings shouldn't be emitted for combinational-read ports--since those ports don't depend on a clock, we shouldn't care what the current implicit clock is.
This is easy enough to fix for the `Mem.read` method, but it's not immediately obvious to me how to fix it for `Mem.apply`, since it's not known at port-declaration time whether the port will be used for writing.
In the meantime, there are obvious workarounds.
**Type of issue**: bug report
**Impact**: API addition (no impact on existing code)
**Development Phase**: request
**Other information**
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
```
val mem = Mem(2, Bool())
val alt_clock = WireInit(clock)
val rdata = WireInit(false.B)
withClock (alt_clock) { rdata := mem(0.U) }
```
**What is the current behavior?**
Warning is emitted.
**What is the expected behavior?**
No warning should be emitted. (More importantly, this should not become an error in 3.6.0, as the message warns.)
**Please tell us about your environment:**
**What is the use case for changing the behavior?**
Contributor guide
Research direction
Start by reproducing the warning with the Mem.read example in the issue, then inspect the Mem.read and Mem.apply paths. The change is done when combinational-read ports do not emit implicit-clock mismatch warnings while write-related behavior remains correct; the issue does not name a test file.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- compilers
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100